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ds07-12537-1e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89670r/670ar series mb89673r/673ar/675r/675ar mb89677ar/p677a/pv670a n outline the mb89670r/670ar series has been developed as a line of proprietary 8-bit, single-chip microcontrollers. in addition to the f 2 mc*-8l family cpu core which can operate at low voltage but at high speed, the microcontrollers contain pheripheral functions such as timers, a serial interface, a 10-bit a/d converter, a uart, an 8/16-bit up/down counter/timer, and an external interrupt. the mb89670r/670ar series is applicable to a wide range of applications from consumer appliances to industrial equipment, including portable devices. *: f 2 mc stands for fujitsu flexible microcontroller. n features ?f 2 mc-8l family cpu core instruction set optimized for controllers ? high-speed processing at low voltage ? minimum execution time: 0.4 m s@3.5 v, 0.8 m s@2.7 v, 2.0 m s@2.2 v ? i/o ports: max. 69 channels (continued) n pac k ag e multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. (mqp-80c-p01) 80-pin ceramic mqfp (mqp-80c-p01) (fpt-80p-m06) (fpt-80p-m11) 80-pin plastic lqfp (fpt-80p-m11) (fpt-80p-m06) 80-pin plastic qfp
2 mb89670r/670ar series (continued) ? timers: 9 channels (mb89675ar/677ar/p677a/pv670a: 12 channels) 8-bit pwm timer: 3 channels (mb89675ar/677ar/p677a/pv670a: 6 channels) (also usable as a reload timer or 8-bit pwm timer) 16-bit timer/counter 21-bit timebase timer 8/16-bit timer (8 bits 2 channels or 16 bits) 8/16-bit up/down counter/timer (8 bits 2 channels or 16 bits) ? 2-channel serial interfaces 8-bit synchronized serial: 1 channel (switchable transfer direction allows communication with various equipment.) uart: 1 channel (internal full-duplex double buffer) ? external interrupts: 8 channels eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? buzzer output ? 10-bit a/d converter input: 8 channels ? low-power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) ? bus interface function including hold and ready functions
3 mb89670r/670ar series n product lineup (continued) mb89673ar mb89675r *1 mb89675ar mb89677ar mb89p677a mb89pv670a classification mass-produced products (mask rom products) one-time prom product (for development) piggyback/ evaluation product (for development) rom size 8 k 8 bits (internal mask rom) 16 k 8 bits (internal mask rom) 32 k 8 bits (internal mask rom) 48 k 8 bits (external rom) ram size 384 8 bits 512 8 bits 1 k 8 bits cpu functions the number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s@10 mhz to 6.4 m s@10 mhz interrupt processing time: 3.6 m s@10 mhz to 57.6 m s@10 mhz ports output ports (n-channel open-drain): 14 (12 also serve as peripherals.) output ports (cmos): 8 (all also serve as peripherals.) i/o ports (n-channel open-drain): 7 (all also serve as peripherals.) i/o ports (cmos): 32 (all also serve as peripherals.) input ports: 8 (all also serve as peripherals.) total: 69 option specify when ordering masking set with eprom programmer setting not possible timebase timer 21 bits (0.81 ms, 3.27 ms, 26.21 ms, 419 ms@10 mhz) 8/16-bit up/down counter/timer 8 bits 2 channels or 16 bits 1 channel timer operation up/down counter operation phase difference counting (double mode, quadruple mode) 16-bit timer/counter 16-bit timer operation 16-bit event counter operation (edge selectable) 8/16-bit timer/counter 8 bits 2 channels or 16 bits 1 channel reload timer operation (toggled output capable) event counter operation 8-bit pwm timer 1, 2 8 bits 2 channels reload timer operation (toggled output capable) 8 bits 2 channels pwm operation (four frequencies fixed) 8 bits 1 channel ppg operation (variable frequency) capable of output switching between 2 channels in any mode 8-bit pwm timer 3, 4, 5, 6 8-bit reload timer operation (toggled output capable) 8-bit pwm operation (four frequencies fixed) capable of output switching between 2 channels in any mode 8-bit serial i/o 8 bits lsb first/msb first selectable one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) mb89673r *1 part number item
4 mb89670r/670ar series (continued) *1: 8-bit pwm timer 4, 5, and 6 are not provided for the mb89673r/mb89675r. *2: the minimum operating voltage varies with the operating frequency, the function, and the connected ice. n package and corresponding products : available : not available * : lead pitch converter sockets (manufacturer: sun hayato co., ltd.) are available 80qf-80qf2-8l-up + (mqp-80c-p01 or fpt-80p-m06) ? for conversion to fpt-80p-m11 80qf-80qf2-8l-dwn inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 note: for more information about each package, see section n package dimensions. mb89673ar mb89675r *1 mb89675ar mb89677ar mb89p677a mb89pv670a uart variable data length (7 or 8 bits) on-chip baud rate generator error detection function on-chip full-duplex double buffer nrz transfer format clk synchrnous/asynchronous data transfer capable 10-bit a/d converter 10 bits 8 channels external interrupt 8 channels (rising edge/falling edge) power supply voltage *2 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use mbm27c512 -20tv package mb89673r mb89675r mb89673ar mb89675ar mb89677ar mb89p677a mb89pv670a fpt-80p-m06 fpt-80p-m11 * mqp-80c-p01 mb89673r *1 part number item
5 mb89670r/670ar series n differences among products 1. memory size before evaluating using the piggyback product, make sure of its differences from the product that will actually be used. take particular care on the following points: ? on the mb89p677a, the program area starts from address 8007 h , while on the mb89677ar and mb89pv670a starts from 8000 h . (on the mb89p677a, the option setting data can be read by reading the addresses 8000 h to 8006 h , while on the mb89677ar and mb89pv670a, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the mb89p677a.) ? the stack area, etc., is set at the upper limit of the ram. ? the external area is used. 2. current consumption ? in the case of the mb89pv670a, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following point: ? options are fixed on the mb89pv670a. 4. differences between the mb89670/670a and mb89670r/670ar series ? memory access area memory access area of both the mb89677a and mb89677ar is the same. the access are of the mb89673 is different from that of the mb89673r and mb89673ar respectively in the external bus mode. see below. address memory area mb89673 mb89673r/673ar 0000 h to 007f h i/o area i/o area 0080 h to 01ff h ram area ram area 0200 h to 027f h external area access prohibited 0280 h to bfff h external area c000 h to dfff h access prohibited e000 h to ffff h rom area rom area
6 mb89670r/670ar series ? electrical specifications/characteristics electrical specifications/characteristics of the mb89673r/673ar/677ar are the same with that of the mb89670/670a series. ? the other specifications both the mb89673r/673ar/677ar and the mb89670/670a series are the same. n correspondence between the mb89670/670a series and mb89670r/670ar series ? the mb89670r/670ar series is the reduction version of the mb89670/670a series. ? the mb89670/670a and mb89670r/670ar sereis consist of the following products: ? differences between the mb89670a/670ar series and mb89670/670r series 8-bit pwm timer 4, 5, and 6 is not provided for the mb89670/670r series. see the table below for the provided 8-bit pwm timer and the corresponding pin for the mb89670a/670ar series and mb89670/670r series. mb89670/ 670a series mb89673 mb89677a mb89p677a mb89pv670a mb89670r/ 670ar series mb89673r mb89673ar mb89675r mb89675ar mb89677ar function pin name for mb89670a/670ar series pin name for mb89670/670r series 8-bit pwm timer 1 p40/pwm00 p40/pwm00, p41/pwm01 8-bit pwm timer 2 p42/pwm10/bz2 p42/pwm10/bz2, p43/pwm11 8-bit pwm timer 3 p30/pwm20 p30/pwm20, p31/pwm21 8-bit pwm timer 4 p31/pwm21 8-bit pwm timer 5 p41/pwm01 8-bit pwm timer 6 p43/pwm11
7 mb89670r/670ar series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p73/ui p72/uo p71/uck p70/bz1 p83 p82 p81 p80 mod0 mod1 x0 x1 v ss rst p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p66/int6 p67/int7 p84 p85 v ss p40/pwm00 p41/pwm01 v cc p42/pwm10/bz2 p43/pwm11 p44/tci p45/tco1 p46/tco2 p47/ec p30/pwm20 p31/pwm21 p32/udz1 p33/udb1 p34/uda1 p35/udz2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p74/sck p75/so p76/si av ss avr av cc p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 p60/int0/adst p61/int1 p62/int2 p63/int3 p64/int4 p65/int5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p21/hak p20/bufc p17/a15 p16/a14 p15/a13 p14/a12 p13/a11 p12/a10 p11/a09 p10/a08 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 p37/uda2 p36/udb2 (fpt-80p-m11) (top view)
8 mb89670r/670ar series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p75/so p74/sck p73/ui p72/uo p71/uck p70/bz1 p83 p82 p81 p80 mod0 mod1 x0 x1 v ss rst p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p64/int4 p65/int5 p66/int6 p67/int7 p84 p85 v ss p40/pwm00 p41/pwm01 v cc p42/pwm10/bz2 p43/pwm11 p44/tci p45/tco1 p46/tco2 p47/ec p30/pwm20 p31/pwm21 p32/udz1 p33/udb1 p34/uda1 p35/udz2 p36/udb2 p37/uda2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p76/si av ss avr av cc p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 p60/int0/adst p61/int1 p62/int2 p63/int3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p17/a15 p16/a14 p15/a13 p14/a12 p13/a11 p12/a10 p11/a09 p10/a08 p07/ad7 p06/ad6 p05/ad5 p04/ad4 p03/ad3 p02/ad2 p01/ad1 p00/ad0 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 100 99 98 97 96 95 94 110 111 112 81 82 83 84 (top view) (fpt-80p-m06) (mqp-80c-p01) each pin inside the dashed line is for the mb89pv670a only. ? pin assignment on package top (mb89pv670a only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 81 n.c. 89 a2 97 n.c. 105 oe /v pp 82a1590a198o4106n.c. 83 a12 91 a0 99 o5 107 a11 84 a7 92 n.c. 100 o6 108 a9 85 a6 93 o1 101 o7 109 a8 86 a5 94 o2 102 o8 110 a13 87 a4 95 o3 103 ce 111 a14 88 a3 96 v ss 104 a10 112 v cc
9 mb89670r/670ar series n pin description (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function lqfp *1 qfp *2 mqfp *3 11 13 x0 a clock oscillator pins 12 14 x1 9 11 mod0 b operating mode selection pins connect directly to v cc or v ss . 10 12 mod1 14 16 rst c reset i/o pin this pin is of a n-ch open-drain output type with pull-up resistor and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 38 to 31 40 to 33 p00/ad0 to p07/ad7 d general-purpose i/o ports when an external bus is used, these ports function as multiplex pins of lower address output and data i/o. 30 to 23 32 to 25 p10/a08 to p17/a15 d general-purpose i/o ports when an external bus is used, these ports function as upper address output pins. 22 24 p20/bufc f general-purpose output port when an external bus is used, this port can also be used as a buffer control output by setting the bctr. 21 23 p21/hak f general-purpose output port when an external bus is used, this port can also be used as a hold acknowledge output by setting the bctr. 20 22 p22/hrq d general-purpose output port when an external bus is used, this port can also be used as a hold request input by setting the bctr. 19 21 p23/rdy d general-purpose output port when an external bus is used, this port functions as a ready input. 18 20 p24/clk f general-purpose output port when an external bus is used, this port functions as a clock output. 17 19 p25/wr f general-purpose output port when an external bus is used, this port functions as a write signal output. 16 18 p26/rd f general-purpose output port when an external bus is used, this port functions as a read signal output. 15 17 p27/ale f general-purpose output port when an external bus is used, this port functions as an address latch signal output.
10 mb89670r/670ar series (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function lqfp *1 qfp *2 mqfp *3 46 48 p30/pwm20 d general-purpose i/o port also serves as the pwm20 output for the 8-bit pwm timer. 45 47 p31/pwm21 d general-purpose i/o port also serves as the pwm21 output for the 8-bit pwm timer. 44 46 p32/udz1 e general-purpose i/o port also serves as the z-phase input for the 8/16-bit up/down counter/timer. 43 45 p33/udb1 e general-purpose i/o port also serves as the b-phase input for the 8/16-bit up/down counter/timer. 42 44 p34/uda1 e general-purpose i/o ports also serves as the a-phase input for the 8/16-bit up/down counter/timer. 41 43 p35/udz2 e general-purpose i/o port also serves as the z-phase input for the 8/16-bit up/down counter/timer. 40 42 p36/udb2 e general-purpose i/o port also serves as the b-phase input for the 8/16-bit up/down counter/timer. 39 41 p37/uda2 e general-purpose i/o port also serves as the a-phase input for the 8/16-bit up/down counter/timer. 55 57 p40/pwm00 d general-purpose i/o port also serves as the pwm00 output for the 8-bit pwm timer. 54 56 p41/pwm01 d general-purpose i/o port also serves as the pwm01 output for the 8-bit pwm timer. 52 54 p42/pwm10/ bz2 d general-purpose i/o port also serves as the pwm10 and the bz2 output for the 8-bit pwm timer. 51 53 p43/pwm11 d general-purpose i/o port also serves as the pwm11 output for the 8-bit pwm timer. 50 52 p44/tci e general-purpose i/o port also serves as the tci input for the 8/16-bit timer/counter. 49 51 p45/tco1 d general-purpose i/o port also serves as the tco1 output for the 8/16-bit timer/counter. 48 50 p46/tco2 d general-purpose i/o port also serves as the tco2 output for the 8/16-bit timer/counter.
11 mb89670r/670ar series (continued) *1: fpt-80p-m11 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function lqfp *1 qfp *2 mqfp *3 47 49 p47/ec e general-purpose i/o port also serves as the input for the16-bit timer/counter. the ec input is of a hysteresis input type. 74 to 67 76 to 69 p50/an0 to p57/an7 i n-ch open-drain output ports also serve as the analog inputs for the 10-bit a/d converter. 66 68 p60/int0/ adst j general-purpose input port the software pull-up resistor is provided. also serves as an external interrupt input (int0) and an 10-bit a/d converter external start-up. this port is of a hysteresis input type. 65 to 59 67 to 61 p61/int1 to p67/int7 j general-purpose input ports a software pull-up resistor is provided. also serve as external interrupt inputs (int1 to int7). these ports are of a hysteresis input type. 4 6 p70/bz1 g n-ch open-drain i/o port also serves as a buzzer output. 3 5 p71/uck k n-ch open-drain i/o port also serves as a uart clock i/o (uck), switchable to cmos. 2 4 p72/uo k n-ch open-drain i/o port also serves as a uart data output (uo), switchable to cmos. 1 3 p73/ui g n-ch open-drain i/o port also serves as a uart data input (ui). 80 2 p74/sck k n-ch open-drain i/o port also serves as the clock i/o (sck) for the 8-bit serial i/o, switchable to cmos. 79 1 p75/so k n-ch open-drain i/o port also serves as the data output (so) for the 8-bit serial i/o, switchable to cmos. 78 80 p76/si g n-ch open-drain i/o port also serves as the data input (si) for the 8-bit serial i/o. 8 to 5, 57, 58 10 to 7, 59, 60 p80 to p83, p85, p84 h n-ch open-drain output ports 53 55 v cc power supply pin 13, 56 15, 58 v ss power supply (gnd) pin 75 77 av cc a/d converter power supply pin use this pin at the same voltage as v cc . 76 78 avr a/d converter reference voltage input pin 77 79 av ss a/d converter power supply pin use this pin at the same voltage as v ss .
12 mb89670r/670ar series ? external eprom pins (mb89pv670a only) pin no. pin name i/o function 82 83 84 85 86 87 88 89 90 91 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 93 94 95 o1 o2 o3 i data input pins 96 v ss o power supply (gnd) pin 98 99 100 101 102 o4 o5 o6 o7 o8 i data input pins 103 ce o rom chip enable pin outputs h during standby. 104 a10 o address output pin 105 oe /v pp o rom output enable pin outputs l at all times. 107 108 109 a11 a9 a8 o address output pins 110 a13 o 111 a14 o 112 v cc o 81 92 97 106 n.c. internally connected pins be sure to leave them open.
13 mb89670r/670ar series n i/o circuit type (continued) type circuit remarks a ? crystal or ceramic oscillation type ? oscillation feedback resistor of approximately 1 m w at 5.0 v b c ? output pull-up resistor (p-ch) of approximately 50 k w at 5.0 v ? hysteresis input d ? cmos output ? cmos inout ? pull-up resistor optional (except p22 and p23) e ? cmos output ? cmos input ? the peripheral is of a hysteresis input type. ? pull-up resistor optional x1 x0 standby control signal r p-ch n-ch n-ch r p-ch p-ch p-ch n-ch r p-ch peripheral port
14 mb89670r/670ar series (continued) type circuit remarks f ? cmos output g ? n-ch open-drain output ? hysteresis input ? pull-up resistor optional h ? n-ch open-drain output i ? n-ch open-drain output ? analog input j ? hysteresis input ? with software pull-up resistor k ? cmos output ? hysteresis input ? pull-up resistor optional p-ch n-ch n-ch r p-ch p-ch n-ch n-ch analog input p-ch r p-ch pull-up control signal p-ch n-ch r p-ch
15 mb89670r/670ar series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 hz to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
16 mb89670r/670ar series n programming to the eprom on the mb89p677a the mb89p677a is an otprom version of the mb89670r/670ar series. 1. features ? 32-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in the eprom mode (when programmed with the eprom programmer) 2. memory space memory space in the eprom mode is diagrammed below. 0000 h 0007 h 7fff h eprom 32 kb 8000 h 8007 h ffff h not available prom 32 kb external area i/o 0480 h 0000 h 0080 h single chip address eprom mode (corresponding addresses on the eprom programmer) ram option area
17 mb89670r/670ar series 3. programming to the eprom in eprom mode, the mb89p677a functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. ? programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h (note that addresses 8007 h to ffff h while operating as a single chip assign to 0007 h to 7fff h in the eprom mode). load option data into addresses 0000 h to 0006 h of the eprom programmer. (for information about each corresponding option, see 7. setting otprom options.) (3) program with the eprom programmer. 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield due to the nature of the blanked otprom microcomputer, bit programming test cant be conducted as fujitsus shipping test. therefore a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 note: depending on the eprom programmer, inserting a capacitor of about 0.1 m f between v pp and v ss or v cc and v ss can stabilize programming operations. part number MB89P677APF mb89p677pfm package qfp-80 qfp-80 compatible socket adapter sun hayato co., ltd. rom-80qf-28dp-8l2 rom-80qf2-28dp-8l program, verify aging +150 c, 48 hrs. data verification assembly
18 mb89670r/670ar series 7. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map notes: each bit is set to 1 as the initialized value. do not write 0 to the vacant bit. the read value of the vacant bit is 1, unless 0 is written to it. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h vacancy readable vacancy readable vacancy readable vacancy readable reset pin output 1: yes 0: no power-on reset 1: yes 0: no oscillation stabilization time 00: 2 4 /f c 10: 2 17 /f c 01: 2 14 /f c 11: 2 18 /f c 0001 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0002 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0003 h p47 pull-up 1: no 0: yes p46 pull-up 1: no 0: yes p45 pull-up 1: no 0: yes p44 pull-up 1: no 0: yes p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes 0004 h vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable vacancy readable 0005 h vacancy readable vacancy readable vacancy readable p74 pull-up 1: no 0: yes p73 pull-up 1: no 0: yes p72 pull-up 1: no 0: yes p71 pull-up 1: no 0: yes p70 pull-up 1: no 0: yes 0006 h vacancy readable vacancy readable vacancy readable vacancy readable p04 to p07 pull-up 1: no 0: yes p00 to p03 pull-up 1: no 0: yes p76 pull-up 1: no 0: yes p75 pull-up 1: no 0: yes
19 mb89670r/670ar series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c512-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 3. memory space memory space in each mode is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c512. (2) load program data into the eprom programmer at 4000 h to ffff h . (3) program to 4000 h to ffff h with the eprom programmer. package adapter socket part number lcc-32(rectangle) rom-32lc-28dp-yg 4000 h 8007 h ffff h not available eprom 48 kb ffff h ram prom 48 kb i/o single chip eprom mode (corresponding address on the eprom programmer) * * external area 0000 h 8000 h 4000 h 0480 h 0080 h 0000 h 8007 h 8000 h address *: note: for the mb89p677a, this area is an option settin g area.
20 mb89670r/670ar series n block diagram 1. block diagram of mb89673r/89675r ram cpu rom uart x0 x1 rst f 2 mc-8l 8 16 8 6 8 8 p00/ad0 to p07/ad7 p10/a08 to p17/a15 mod0 mod1 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc p80 to p85 p60/int0/adst to p67/int7 p50/an0 to p57/an7 avr 8 8 p37/uda2 p36/udb2 p35/udz2 p34/uda1 p33/udb1 p32/udz1 p47/ec p46/tco2 p45/tco1 p44/tci p43/pwm11 p42/pwm10/bz2 p41/pwm01 p40/pwm00 p31/pwm21 p30/pwm20 p73/ui p72/uo p71/uck p76/si p75/so p74/sck p70/bz1 av cc av ss oscillator clock controller reset circuit (wdt) cmos i/o port external bus interface cmos output port n-ch open-drain output port 10-bit a/d converter input port external interrupt internal data bus timebase timer cmos i/o port 16-bit up/down counter/timer 8-bit up/down counter/timer 16-bit timer/counter 8/16-bit timer 8-bit timer 8-bit timer 2-channel 8-bit pwm timer 8-bit timer #2 8-bit timer #1 8-bit pwm timer #3 8-bit serial i/o buzzer output n-ch open-drain i/o port 8-bit up/down counter/timer the other pins v cc , v ss , mod0, mod1
21 mb89670r/670ar series 2. block diagram of mb89673ar /89675ar/89677ar/89p677a/89pv670a the other pins v cc , v ss , mod0, mod1 ram cpu rom x0 x1 rst f 2 mc-8l 8 16 8 6 8 8 p00/ad0 to p07/ad7 p10/a08 to p17/a15 mod0 mod1 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc p80 to p85 p60/int0/adst to p67/int7 p50/an0 to p57/an7 8 8 p37/uda2 p36/udb2 p35/udz2 p34/uda1 p33/udb1 p32/udz1 p47/ec p46/tco2 p45/tco1 p44/tci p40/pwm00 p42/pwm10/bz2 p76/si p75/so p74/sck p70/bz1 p30/pwm20 p31/pwm21 p41/pwm01 p43/pwm11 uart p73/ui p72/uo p71/uck avr av cc av ss oscillator clock controller reset circuit (wdt) cmos i/o port external bus interface cmos output port n-ch open-drain output port 10-bit ad converter input port external interrupt internal data bus timebase timer cmos i/o port 16-bit up/down counter/timer 8-bit up/down counter/timer 16-bit timer/counter 8/16-bit timer 8-bit timer 8-bit timer 8-bit pwm timer #3 8-bit pwm timer #4 8-bit pwm timer #5 8-bit pwm timer #6 2-channel 8-bit pwm timer 8-bit timer #1 8-bit timer #2 8-bit serial i/o buzzer output n-ch open-drain i/o port 8-bit up/down counter/timer
22 mb89670r/670ar series n cpu core 1. memory space the microcontrollers of the mb89670r/670ar series offer 64 kbytes of memory for storing all of i/o, data, and program areas. the i/o area is allocated at the lowest address. the data area is allocated immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is allocated from exactly the opposite end of i/o area, that is, near the highest address. the tables of interrupt reset vectors and vector call instructions are allocated from the highest address within the program area. the memory space of the mb89670r/670ar series is structured as illustrated below. ? memory space rom 8 kb ffff h 0080 h 0000 h i/o mb89673r mb89673ar e000 h 0100 h ram register 0200 h external area ** 8007 h 8000 h mb89pv670a ffff h 0080 h 0000 h i/o external area 0100 h 0200 h 0480 h 4000 h ram 8000 h 8007 h * register programmable rom *: since addresses 8000 h to 8006 h for the mb89p677a comprise an option area, pay attention to use this area for the other products in this series. mb89677ar mb89p677a programmable rom ffff h 0080 h 0000 h i/o 0100 h ram register 0200 h 0480 h external area 8007 h 8000 h option prom (one-time prom product)* mb89675r mb89675ar 512 b 1 kb 1 kb 384 b not available rom 16 kb 32 kb 48 kb ffff h 0080 h 0000 h i/o 0100 h ram register 0200 h 0280 h 0280 h external area external area external area not available 8007 h c000 h c000 h 8000 h
23 mb89670r/670ar series 2. registers the f 2 mc-8l family has two types of registers; dedicated hardware registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating the instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1, il0 = 11 the other bit values are indeterminate. initial value ? structure of the program status register vacancy h i il1, il0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
24 mb89670r/670ar series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to 0 otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, il0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes 1 as the result of an arithmetic operation. cleared to 0 when the bit is cleared to 0. z-flag: set to 1 when an arithmetic operation results in 0. cleared to 0 otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to 0 if the overflow does not occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 ? rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
25 mb89670r/670ar series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are of 8 bits each and allocated in the register banks of the memory. one bank contains eight registers and up to 32 banks can be used on every product of the mb89670r/670ar series. the bank currently in use is indicated by the register bank pointer (rp). ? register bank configuration this address = 0100 h + 8 (rp) memory area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
26 mb89670r/670ar series n i/o map (continued) address read/write register abbreviation register name 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (w) bctr external bus pin control register 06 h (vacancy) 07 h (r/w) sycc system clock control register 08 h (r/w) stbc standby control register 09 h (r/w) wdtc watchdog timer control register 0a h (r/w) tbtc timebase timer control register 0b h (vacancy) 0c h (r/w) pdr3 port 3 data register 0d h (w) ddr3 port 3 data direction register 0e h (r/w) pdr4 port 4 data register 0f h (w) ddr4 port 4 data direction register 10 h (r/w) pdr5 port 5 data register 11 h (r) pdr6 port 6 data register 12 h (r/w) ppcr port 6 pull-up control register 13 h (r/w) pdr7 port 7 data register 14 h (r/w) pdr8 port 8 data/port 7 swiching register 15 h (r/w) bzcr buzzer register 16 h (r/w) cntr #3 pwm control register #3 17 h (r/w) comp #3 pwm compare register #3 18 h (r/w) tmcr 16-bit timer control register 19 h (r/w) tchr 16-bit timer count register (h) 1a h (r/w) tclr 16-bit timer count register (l) 1b h (vacancy) 1c h (r/w) smr serial mode register 1d h (r/w) sdr serial data register 1e h to 1f h (vacancy)
27 mb89670r/670ar series (continued) address read/write register abbreviation register name 20 h (r/w) adc1 a/d converter control register 1 21 h (r/w) adc2 a/d converter control register 2 22 h (r/w) adch a/d converter data register h 23 h (r/w) adcl a/d converter data register l 24 h (r/w) t2cr timer 2 control register 25 h (r/w) t1cr timer 1 control register 26 h (r/w) t2dr timer 2 data register 27 h (r/w) t1dr timer 1 data register 28 h (r/w) cntr1 pwm 1 control register 29 h (r/w) cntr2 pwm 2 control register 2a h (r/w) cntr3 pwm 3 control register 2b h (w) comr2 pwm 2 compare register 2c h (w) comr1 pwm 1 compare register 2d h to 2f h (vacancy) 30 h (r) (w) udcr1 rcr1 up/down counter register 1 reload compare register1 31 h (r) (w) udcr2 rcr2 up/down counter register 2 reload compare register2 32 h (r/w) ccra1 counter control register a1 33 h (r/w) ccra2 counter control register a2 34 h (r/w) ccrb1 counter control register b1 35 h (r/w) ccrb2 counter control register b2 36 h (r/w) csr1 counter status register 1 37 h (r/w) csr2 counter status register 2 38 h (r/w) eic1 external interrupt 1 control register 1 39 h (r/w) eic2 external interrupt 1 control register 2 3a h (r/w) eie2 external interrupt 2 control register 3b h (r/w) eif2 external interrupt 2 flag register 3c h to 3f h (vacancy)
28 mb89670r/670ar series (continued) * : for the mb89673r/675r, these are (vacancies). note: do not use (vacancies). address read/write register abbreviation register name 40 h (r/w) usmr uart serial mode register 41 h (r/w) uscr uart serial rate control register 42 h (r/w) ustr uart status register 43 h (r) (w) rxdr txdr uart receiving data register uart transmitting data register 44 h (vacancy) 45 h (r/w) rrdr baud rate generator reload data register 46 h to 47 h (vacancy) 48 h * (r/w) cntr #4 pwm control register #4 49 h * (r/w) comp #4 pwm compare register #4 4a h * (r/w) cntr #5 pwm control register #5 4b h * (r/w) comp #5 pwm compare register #5 4c h * (r/w) cntr #6 pwm control register #6 4d h * (r/w) comp #6 pwm compare register #6 4e to 7b h (vacancy) 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level setting register 2 7e h (w) ilr3 interrupt level setting register 3 7f h (vacancy)
29 mb89670r/670ar series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set at the same voltage. take care that avr does not exceed av cc + 0.3 v and av cc does not exceed v cc , such as when power is turned on. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rated value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v * av cc v ss C 0.3 v cc + 0.3 v * a/d converter reference input voltage avr v ss C 0.3 v cc + 0.3 v avr must not exceed av cc + 0.3 v. input voltage v i v ss C 0.3 v cc + 0.3 v output voltage v o1 v ss C 0.3 v cc + 0.3 v except p80 to p85 v o2 v ss C 0.3 v ss + 7.0 v p80 to p85 l level maximum output current i ol 20ma l level average output current i olav1 4ma average value (operating current operating rate) i olav2 8ma average value (operating current operating rate) p80 to p85 l level total maximum output current ? i ol 100ma l level total average output current ? i olav 40ma average value (operating current operating rate) h level maximum output current i oh C20ma h level average output current i ohav C4ma average value (operating current operating rate) h level total maximum output current ? i oh C50ma h level total average output current ? i ohav C20ma average value (operating current operating rate) power consumption p d 300mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
30 mb89670r/670ar series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. parameter symbol rated value unit remarks min. max. power supply voltage v cc av cc 2.2* 6.0 v normal operation assurance range mb89673r/673ar/675r/675ar/677ar 2.7* 6.0 v normal operation assurance range mb89pv670a/p677a 1.5 6.0 v retains the ram state in the stop mode a/d converter reference input voltage avr 0.0 av cc v operating temperature t a C40 +85 c figure 1 operating voltage vs. clock operating frequency 1 2 3 4 5 6 1.0 10.0 operation assurance range 5.0 clock operating frequency (mhz) note: the shaded area is additional operatin g assurance ran g e only for the mb89673r/673ar/675r/675ar/677ar. 2.0 3.0 4.0 6.0 7.0 8.0 9.0 a/d converter accuracy assured in the v cc = av cc = 3.5 v to 6.0 v range. 4.0 0.4 0.8 2.0 minimum execution time ( m s) operating voltage (v)
31 mb89670r/670ar series the horizontal line of the graph in the figure 1 indicates the operating frequency of the external oscillator and the lower horizontal line indicates the min. instruction execution time = 4/f c . in the case of changing the operating clock with the clock gear function, be sure to convert it into the min. instruction execution time on the lower horizontal line since the operating voltage range is dependent on the min. instruction execution time. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand.
32 mb89670r/670ar series 3. dc characteristics (av cc = v cc = 5.0 v 10 %, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition rated value unit remarks min. typ. max. h level input voltage v ih p00 to p07, p10 to p17, p30 to p37, p40 to p47 0.7 v cc ? v cc + 0.3 v p32 to p37, p44, and p47 are of a port input type. v ihs rst , mod0, mod1, p32 to p37, p44, p47, p60 to p67, p70 to p76 0.8 v cc ? v cc + 0.3 v p32 to p37, p44, and p47 are of a peripheral input type. l level input voltage v il p00 to p07, p10 to p17, p30 to p37, p40 to p47 v ss - 0.3 ? 0.3 v cc v p32 to p37, p44, and p47 are of a port input type. v ils rst , mod0, mod1, p32 to p37, p44, p47, p60 to p67, p70 to p76 v ss - 0.3 ? 0.2 v cc v p32 to p37, p44, and p47 are of a peripheral input type. open-drain output pin applied voltage v d p80 to p85 v ss - 0.3 ? v ss + 6.0 v h level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p71, p72, p74, p75 i oh = C2.0 ma 4.0 ?? v l level output voltage v ol1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p76 i ol = 4.0 ma ?? 0.4 v v ol2 p80 to p85 i ol = 10 ma ?? 0.5 v v ol3 rst i ol = 4.0 ma 0.4 v input leakage current (hi-z output leakage current) i li1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p76, mod0, mod1 0.0 v < v i < v cc 5 m a without pull-up resistor option i li2 p80 to p85 0.0 v < v i < v cc 1 m a pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p47, p60 to p67, p70 to p76, rst v i = 0.0 v 25 50 100 k w with pull-up resistor option
33 mb89670r/670ar series (continued) (av cc = v cc = 5.0 v 10 %, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: the measurement conditions of the power supply current are as follows. the external clock is used. the output pins are open. v cc is upon the condition above the table. *2: for information on t inst , see (4) instruction cycle in 4. ac characteristics. note: the current consumption of connected eprom and ice is not considered on mb89pv670a. parameter symbol pin name condition rated value unit remarks min. typ. max. power supply current *1 i cc1 v cc f c = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 1220ma i cc2 f c = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 1 2ma mb89673r/ 673ar/ 675r/675ar/ 677ar/ pv670a 1.5 2.5 ma mb89p677a i ccs1 f c = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 3 7ma i ccs2 f c = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 1 1.5 ma i cch v cc = 3.0 v t a = +25 c stop mode 1ma i a av cc f c = 10 mhz when a/d converter starts 6 8ma i ah f c = 10 mhz t a = +25 c when a/d converter is at a stop 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10pf sleep mode
34 mb89670r/670ar series 4. ac characteristics (1) reset timing (av cc = v cc = 5.0 v 10 %, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (2) specifications for power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition rated value unit remarks min. max. rst l pulse width t zlzh 48 t hcyl ns parameter symbol condition rated value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1ms min. internal time to next power-on reset 0.2 v cc 0.2 v cc 0.8 v cc rst t zlzh 0.2 v 0.2 v 2.0 v v cc 0.2 v t r t off
35 mb89670r/670ar series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) (4) instruction cycle (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition rated value unit remarks min. max. clock frequency f c x0, x1 110mhz clock cycle time t xcyl x0, x1 100 1000 ns input clock pulse width p wh p wl x0 20 ns external clock input clock rising/falling time t cr t cf x0 10 ns external clock parameter symbol rated value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f c , 8/f c , 16/f c , 64/f c m s (4/f c ) t inst = 0.4 m s when operating at f c = 10 mhz ? clock timing conditions 0.2 v cc 0.8 v cc x0 0.2 v cc 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic resonator is used when an external clock is used open f c c 1 c 2 t xcyl p wh p wl t cr t cf ? clock configurations
36 mb89670r/670ar series (5) clock output timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition rated value unit remarks min. max. cycle time t cyc clk 1/2 t inst * m s clk - ? clk t chcl clk 1/4 t inst C 0.07 1/4 t inst m s 2.4 v clk 0.8 v t cyc 2.4 v t chcl
37 mb89670r/670ar series (6) bus read timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition rated value unit remarks min. max. valid address ? rd time t avrl rd , a15 to a08, ad7 to ad0 1/4 t inst * C 0.06 m s rd pulse width t rlrh rd 1/2 t inst *C 0.02 m s valid address ? data read time t avdv ad7 to ad0, a15 to a08 1/2 t inst * m s no wait rd ? data read time t rldv rd , ad7 to ad0 1/2 t inst *C 0.08 m s no wait rd - ? data hold time t rhdx ad7 to ad0, rd 0ns rd - ? ale - time t rhlh rd , ale 1/4 t inst * C 0.04 m s rd - ? address loss time t rhax rd , a15 to a08 1/4 t inst * C 0.04 m s rd ? clk - time t rlch rd , clk 1/4 t inst * C 0.04 m s clk ? rd - time t clrh rd , clk 0ns rd ? bufc time t rlbl rd , bufc C5 ns bufc - ? valid address time t bhav a15 to a08, ad7 to ad0, bufc 5ns ale ad a rd bufc clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v t rhdx t bhav t rlbl t clrh t rhlh t avdv t rlch t rhax t rldv t avrl t rlrh
38 mb89670r/670ar series (7) bus write timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: these characteristics are also applicable to the bus read timing. *2: for information on t inst , see (4) instruction cycle. parameter symbol pin name condition rated value unit remarks min. max. valid address ? ale time t avll ad7 to ad0, ale, a15 to a08 1/4 t inst * 2 C 0.064 m s ale time ? address loss time t llax ad7 to ad0, ale, a15 to a08 5 *1 ns valid address ? wr time t avwl wr , ale 1/4 t inst * 2 C 0.06 m s wr pulse width t wlwh wr 1/2 t inst * 2 C 0.02 m s writing data ? wr - time t dvwl ad7 to ad0, wr 1/2 t inst * 2 C 0.06 m s wr - ? address loss time t whax wr , a15 to a08 1/4 t inst * 2 C 0.04 m s wr - ? data hold time t whdx ad7 to ad0, wr 1/4 t inst * 2 C 0.04 m s wr - ? ale - time t whlh wr , ale 1/4 t inst * C 0.04 m s wr ? clk - time t wlch wr , clk 1/4 t inst * 2 C 0.04 m s clk ? wr - time t clwh wr , clk 0ns ale pulse width t lhll ale 1/4 t inst * 2 C 0.035 m s ale ? clk - time t llch ale, clk 1/4 t inst * 2 C 0.03 m s ale ad a wr clk 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t clwh 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t llax t wlwh t dvwh t lhll t llch t whlh t avll t whdx t wlch t whax t avwl
39 mb89670r/670ar series (8) ready input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : these characteristics are also applicable to the read cycle. parameter symbol pin name condition rated value unit remarks min. max. rdy valid ? clk - time t yvch rdy, clk 60 ns * clk - ? rdy loss time t chyx rdy, clk 0 ns * clk ale ad a wr rdy address t yvch t chyx t yvch t chyx 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 2.4 v note: the bus cycle is also extended in the read cycle in the same manner. data
40 mb89670r/670ar series (9) serial i/o timing (av cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition rated value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s ? external shift clock mode 0.8 v 2.4 v t scyc 2.4 v t slov 0.2 v cc t shix 0.8 v 0.8 v t ivsh 0.8 v cc 0.2 v cc 0.8 v cc sck so si ? internal shift clock mode t slsh 2.4 v t slov t shix 0.8 v cc 0.8 v t ivsh 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc t shsl 0.8 v cc 0.2 v cc 0.2 v cc sck so si
41 mb89670r/670ar series (10) peripheral input timing (av cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin name condition rated value unit remarks min. max. peripheral input h pulse width 1 t ilih1 tci 1 t inst * m s peripheral input l pulse width 1 t ihil1 tci 1 t inst * m s peripheral input h pulse width 2 t ilih2 ec, int0 to int7 2 t inst * m s peripheral input l pulse width 2 t ihil2 ec, int0 to int7 2 t inst * m s peripheral input h pulse width 3 t ilih3 adst a/d mode 64 t inst * m s peripheral input l pulse width 3 t ihil3 adst 64 t inst * m s peripheral input h pulse width 3 t ilih3 adst sense mode 64 t inst * m s peripheral input l pulse width 3 t ihil3 adst 64 t inst * m s 0.2 v cc 0.8 v cc t ihil2 0.8 v cc ec int0 to int7 0.2 v cc t ilih2 0.2 v cc 0.8 v cc t ihil3 0.8 v cc adst 0.2 v cc t ilih3 0.2 v cc 0.8 v cc t ihil1 0.8 v cc tci 0.2 v cc t ilih1
42 mb89670r/670ar series (11) up/down counter input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin name condition rated value unit remarks min. max. ain input 1 pulse width t ahl p33, p34, p36, p37 2 t inst * m s ain input 0 pulse width t all 2 t inst * m s bin input 1 pulse width t bhl 2 t inst * m s bin input 0 pulse width t bll 2 t inst * m s ain - ? bin - time t aubu 1 t inst * m s bin - ? ain time t buad 1 t inst * m s ain ? bin time t adbd 1 t inst * m s bin ? ain - time t bdau 1 t inst * m s bin - ? ain - time t buau 1 t inst * m s ain - ? bin time t aubd 1 t inst * m s bin ? ain time t bdad 1 t inst * m s ain ? bin - time t adbu 1 t inst * m s zin input 1 pulse width t zhl p32, p35 1 t inst * m s zin input 0 pulse width t zll 1 t inst * m s
43 mb89670r/670ar series bin t ahl ain t all t aubu t buad t adbd t bdau t bhl t bll ain t bhl bin t bll t buau t aubd t bdad t adbu t ahl t all zin t zhl t zll 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc
44 mb89670r/670ar series 5. a/d converter electrical characteristics (av cc = v cc = 3.5 v to 6.0 v, f c = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) 6. notes on using a/d converter ? the smaller | avr C av ss |, the greater the error would become relatively. ? the output impedance of the external circuit for the analog input must satisfy the following conditions: output impedance of the external circuit < approx. 10 k w if the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 6 m s at 10 mhz oscillation). an analog input equivalent circuit is shown below. parameter symbol pin name rated value unit remarks min. typ. max. resolution 10 bit linearity error 2.0 lsb av cc = avr = v cc differential linearity error 1.5 lsb total error 3.0 lsb zero transition voltage v ot an0 to an7 av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst an0 to an7 avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 4 lsb a/d mode conversion time 13.2 m s at 10 mhz oscillation sense mode conversion time 7.2 m s at 10 mhz oscillation analog port input current i ain an0 to an7 10 m a analog input voltage an0 to an7 0avrv reference voltage avr 0 av cc v reference voltage supply current i r avr 200 ?m a avr = 5.0 v ? analog input equivalent circuit comparator c 60 pf r 3 k w sample hold circuit closes for approx. 15 instruction cycles after starting a/d conversion. analog channel selector r 10 k w is recommended. analog input pin if r > 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. microcontrollers internal circuit
45 mb89670r/670ar series since the a/d converter contains a sample hold circuit, the level of the analog input pin might not stabilize within the sampling period after starting a/d, resulting in inaccurate a/d conversion values, if the input impedance to the analog pin is too high. be sure to maintain an appropriate input impedance to the analog pin. it is recommended to keep the input impedance to the analog pin from exceeding 10 k w . if it exceeds 10 k w , it is recommended to connect a capacitor of approx. 0.1 m f to the analog input pin. except for the sampling period after starting a/d, the input leakage current of the analog input pin is less than 10 m a. 7. a/d converter glossary ? resolution analog-change that are identifiable with the a/d converter. ? linearity error the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? 11 1111 1110) from actual conversion characteristics ? differential linearity error the deviation of the input voltage needed to change the output code by 1 lsb from the theoretical voltage ? total error the difference between theoretical and actual conversion values, caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. (continued) 3ff 3fe 3fd 004 003 002 001 v ot 0.5 lsb av ss 1 lsb 1.5 lsb v fst avr 3ff 3fe 3fd 004 003 002 001 av ss v nt avr {1 lsb n + 0.5 lsb} 1 lsb = v fst C v ot 1022 (v) v nt C {1 lsb n + 0.5 lsb } 1 lsb theoreticall i/o characteristics digital output analog input digital output total error actual conversion value actual conversion value theoretical value analog input total error of digital output n =
46 mb89670r/670ar series (continued) 3ff 3fe 3fd 004 003 002 001 av ss v nt avr {1 lsb n + v ot } v nt C {1 lsb n + v ot } 1 lsb 004 003 002 001 av ss 3ff 3fe 3fd 3fc avr av ss avr v nt v (n+1)t C v nt 1 lsb C 1 zero transition error digital output analog input actual conversion value theoretical value actual conversion value v ot (actual measured value) full-scale transition error digital output analog input actual conversion value actual conversion value v fst (actual measured value) theoretical value differential linearity error digital output analog input v (n + 1)t actual conversion value actual conversion value theoretical value n + 1 n n C 1 n C 2 linearity error digital output analog input v ot (actual measured value) v fst (actual measured value) actual conversion value theoretical value actual conversion value linearity error of digital output n = differential linearity error of digital output n =
47 mb89670r/670ar series n example characteristics (1) l level output voltage (2) h level output voltage (3) h level input voltage/l level input voltage (cmos input) 0.0 1.0 v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 v cc ?v oh (v) t a = +25 c v cc v oh vs. i oh 012 3 456 7 5.0 v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v cc (v) v in (v) t a = +25 c 123 456 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v v ol1 (v) 0 i ol (ma) v ol1 vs. i ol 2 4 6 8 10 12 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v v ol2 (v) 0 i ol (ma) v ol2 vs. i ol
48 mb89670r/670ar series (5) power supply current (external clock) 012 3 456 7 5.0 v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils v cc (v) v in (v) t a = +25 c 10 8 6 4 2 i ccs (ma) v cc (v) 3456 i ccs vs. v cc i ccs1 i ccs2 0 v cc (v) 234 5 6 10 1 100 1000 r pull (k w ) r pull vs. v cc 50 500 t a = +25 c (6) pull-up resistance i cc (ma) v cc (v) 34 5 6 i cc vs. v cc i cc1 i cc2 0 20 15 10 5 v ihs : threshold when input voltage in hysteresis characteristics is set to h level v ils : threshold when input voltage in hysteresis characteristics is set to l level (4) h level input voltage/l level input voltage (hysteresis input)
49 mb89670r/670ar series n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ? others table 1 lists symbols used for notation of instructions. table 1 instruction symbols (continued) symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8/3 bits) rel branch relative address (8 bits) @ register indirect (e.g.: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits)
50 mb89670r/670ar series (continued) columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions. an instruction cycle consists of 2 machine cycles. #: the number of bytes operation: operation of an instruction tl, th, ah: a changed contents of the tl, th and ah when instruction is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the upper 8 bits of the data in the operation. ? al and ah must become the contents of al and ah each prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: e.g.: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents at address is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the contents addressed by the contents at address is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
51 mb89670r/670ar series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, the data transfered at t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
52 mb89670r/670ar series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
53 mb89670r/670ar series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
54 mb89670r/670ar series n instruction map 0123456789 abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a@,ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep ,#d8 cmp @ep ,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h l h
55 mb89670r/670ar series n mask options n ordering information no. part number mb89673r mb89673ar mb89675r mb89675ar mb89677ar mb89p677a mb89pv670a specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p10 to p17, p30 to p37, p40 to p47, p70 to p76 selectable by pin selectable by pin fixed to without pull-up resistor 2 pull-up resistors p00 to p03 selectable by pin selectable in 4-pin unit 3 pull-up resistors p04 to p07 selectable by pin selectable in 4-pin unit 4 power-on reset with power-on reset without power-on reset selectable selectable fixed to with power-on reset 5 oscillation stabilization time selection (at 10 mhz) approx. 2 18 /f c (approx. 26.2 ms) approx. 2 17 /f c (approx. 13.1 ms) approx. 2 14 /f c (approx. 1.6 ms) approx. 2 4 /f c (approx. 0 ms) f c : clock frequency selectable selectable fixed to approx. 2 18 /f c (approx. 26.2 ms) 6 reset pin output with reset output without reset output selectable selectable fixed to with reset output part number package remarks mb89673rpf mb89673arpf mb89675rpf mb89675arpf mb89677arpf MB89P677APF 80-pin plastic qfp (fpt-80p-m06) mb89673rpfm mb89673arpfm mb89675rpfm mb89675arpfm mb89677arpfm MB89P677APFm 80-pin plastic lqfp (fpt-80p-m11) mb89pv670acf 80-pin ceramic mqfp (mqp-80c-p01)
56 mb89670r/670ar series n package dimensions "a" lead no. (.031.008) 0.800.20 0.30(.012) 0.25(.010) 80 65 64 41 40 25 24 1 22.300.40(.878.016) 18.40(.724)ref m 0.16(.006) (.014.004) 0.350.10 0.80(.0315)typ (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.00(.472) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.58(.023)max 0.10(.004) "b" 1994 fujitsu limited f80010s-3c-2 c dimensions in mm (inches) 80-pin plastic qfp (fpt-80p-m06) (mounting height)
57 mb89670r/670ar series c 1995 fujitsu limited f80016s-1c-3 0.13(.005) m 0.10(.004) 1 pin index .059 ?.004 +.008 ?0.10 +0.20 1.50 "a" details of "a" part 0 10? 0.500.20 0.100.10 (.004.004) (.020.008) (stand off) 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.65(.0256)typ 0.300.10 (.012.004) 0.127 +0.05 ?0.02 +.002 ?.001 .005 12.35 15.00 (.486) ref (.591) nom 20 21 40 1 80 61 41 60 lead no. (mounting height) 80-pin plastic lqfp (fpt-80p-m11) dimensions in mm (inches)
58 mb89670r/670ar series dimensions in mm (inches) +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 index typ 4.50(.177) typ 6.00(.236) index area 1.50(.059)typ 1.00(.040)typ typ 1.00(.040) typ 1.50(.059) (.0315.010) 0.800.25 1.20 .047 12.00(.472)typ (.0315.010) 0.800.25 ref 18.40(.724) (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 8.70(.343) (.006.002) 0.150.05 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m80001sc-4-2 c dimensions in mm (inches) 80-pin ceramic mqfp (mqp-80c-p01)
59 mb89670r/670ar series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9803 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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